TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks By Marco Bertuletti, ETH April 8, 2026
Assertain: Automated Security Assertion Generation Using Large Language Models By Shams Tarek, University of Florida, Gainesville April 6, 2026
VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems By Akram Ben Ahmed, National Institute of Advanced Industrial Sciences and Technology April 3, 2026
A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators By Luca Colagrande, ETH Zurich April 1, 2026
Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification By Antonino Armato, Robert Bosch March 31, 2026
SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research By Zehra Karadağ, Ruhr University Bochum March 30, 2026
An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks By Mohammad Javad Sekonji, Shahid Bahonar University of Kerman March 23, 2026
Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings By Jie Lei, Universitat Politècnica de València March 20, 2026
A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency By Junyi Liu, University of Maryland March 18, 2026
SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks By Kanishka Gunawardana, University of Peradeniya March 13, 2026
An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS By Qiyue Chen, University of Science and Technology of China March 12, 2026
A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA By Neelesh Gupta, University of Southern California March 11, 2026
VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration By Max Wipfli, ETH Zurich March 9, 2026
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link By Yichao Zhang, ETH Zurich March 3, 2026
AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance By Seungkwan Kang, KAIST February 27, 2026
LUTstructions: Self-loading FPGA-based Reconfigurable Instructions By Philippos Papaphilippou, University of Southampton February 25, 2026
CQ-CiM: Hardware-Aware Embedding Shaping for Robust CiM-Based Retrieval By Xinzhao Li, Villanova University February 24, 2026
GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon By Arya Tschand, Harvard University February 23, 2026
Creating a Frequency Plan for a System using a PLL By Julian Jenkins, Perceptia Devices February 18, 2026