SOCAMM: Modernizing Data Center Memory with LPDDR6/5X

By Frank Ferro

April 9, 2026

Small Outline Compression-Attached Memory Module (SOCAMM) has made its way into the data center as an alternative to external CPU memory, due to its high performance, low power, memory capacity, and scalability. The latest CPUs used in AI factories rely on SOCAMM2 to significantly increase memory bandwidth and capacity while at the same time consuming less than half the power of traditional DDR configurations. At this memory speed and capacity, the CPU and GPU work more efficiently together, especially when performing agentic AI workloads.

Addressing Bandwidth, Capacity, and Power

As large language models (LLMs) evolve, there is a growing demand for more advanced AI training and inference hardware to support their capabilities. The compute power for these LLMs is becoming increasingly constrained by memory bandwidth, capacity, latency, and power. Adding more processors to meet escalating computing demands will have diminishing returns without an adequate memory subsystem.

Addressing this need for performance, SOCAMM2 is based on LPDDR5X DRAMs with speeds up to 9.6Gbps per bit. At this speed, a single LPDDR5X DRAM delivers a bandwidth of 38GB/s (9.6Gbps x 32-bits). The SOCAMM2 is constructed using four LPDDR5X DRAM packages for a total memory bandwidth of 154GB/s per SOCAMM2. At this speed, an 8-channel CPU used in an AI factory will have 1.2TB/s of bandwidth.

Memory capacity is also critical to support the latest AI workloads that drive large model parameters, expansive context windows, and the need for concurrency. A single SOCAMM2 supports a capacity ranging from 128GB to 256GB. At 256GB, the same 8-channel CPU will have 2TB of total capacity.

Power consumption is a growing challenge in the data center, not only for operating costs but also for compute efficiency. Memory can account for up to 40% of a data center compute platform's power. As higher memory bandwidth and capacity are needed to service these LLMs, the power consumption may require moving from air cooling to liquid cooling. Liquid cooling is typically reserved for high-end (high-cost) systems, so minimizing power while simultaneously increasing performance is critical, especially for mid-range systems to maintain air cooling. According to a study by Micron, memory power can be reduced by 75% under certain workload conditions, with 10% better overall system power efficiency (performance/watt) using LPDDR5X memory.

Under the Hood

At the chip level, the CPU requires four LPDDR5X physical layers (or PHYs) and memory controllers for each SOCAMM. Systems with eight SOCAMMs require 32 LPDD5X PHYs and memory controllers for a total of 1,024 data signals, plus the associated power, ground, and control signals (for comparison, HBM3 has 1024 data bits). Routing all these signals out of the package and across the PCB to the SOCAMM is a significant physical design challenge. Maintaining peak performance of 9.6Gbps over this difficult channel requires a high-performance PHY along with careful design of the bump map and package to minimize effects like crosstalk and insertion loss.

LPDDR5X DRAMs were originally intended for use in mobile devices, including cell phones, laptops, PCs, and tablets. In these applications, the DRAM is very close to the processor to minimize space and power, so the DRAM has a very short channel using package-on-package (POP) technology. In the case of the SOCAMM, the DRAM requires discrete packaging and will sit several inches from the processor. Again, it is critical to have a robust PHY and expert physical design capabilities to meet the signal integrity requirements in this environment.

In support of customers building these AI platforms, Cadence has demonstrated SOCAMM2 performance at 9.6Gbps. The hardware is built on an LPDDR6/5X combination PHY and memory controller that was announced in July 2025 in conjunction with JEDEC's announcement of the LPDDR6 specification. The PHY and controller support LPDDR6 speeds of 14.4Gbps and LPDDR5X speeds of 10.7Gbps. Specifically designed for data center applications, the PHY demonstrates the robustness, signal integrity, and scalability needed for these systems. In addition, Cadence package, PCB, and signal integrity experts work closely with customers to optimize system performance to achieve the required bandwidth.

With its high performance, low power, and scalability, LPDDR5X used in SOCAMM2 is reshaping data center memory architectures to support the latest agentic AI workloads. Of course, the demand for memory bandwidth will not let up anytime soon. LPDDR6, the latest-generation LPDDR memory, has been designed with features specific to data center AI applications, including more performance, better power management, more capacity, and RAS (reliability, availability, serviceability) features that are essential for robust performance (see LPDDR6: A New Standard and Memory Choice for AI Data Center Applications).

To learn more about these products, please visit A Family of High-Speed On-Chip Memory Interface IP at cadence.com.